- 32-bit RISC/DSP processor
- Parallelism of ALU, DSP unit and Load/Store unit
- 16, 32, 48-bit instructions
- 64 local, 26 global registers
- Local regs organized in circular
- 4 GByte memory address space
- Separate I/O address space
- 16 kByte RAM on-chip (1 cycle)
- On-chip instruction cache
- Separate address and data bus
- 32-bit timer and watchdog timer
- Comprehensive controller for DRAM, SDRAM
- Programmable bus timing for all
- Clock frequency:
- i.e. E1-32XSR 120 MHz in 0.25µm
- Implementations in 0.18µm up to 220 MHz - On-chip PLL (8:1,4:1,2:1,1:1,0.5:1)
- Static design
- 120 MIPS and up to 480 MOPS in 0.25 µm; 220 MIPS and up to 880 MOPS in 0.18µm
- up to 2445 MIPS/Watt
- 1 k complex FFT in 0.25 ms
- 4 cycle MPY (32 x 32 bit)
- 1 cycle MPY (16 x 16 bit)
- 1 cycle multiply-add (pipelined)
- 1 cycle MOV, ADD, CMP, SHIFT
- 1 cycle DRAM read or write (pipelined)
- Glue-less memory- and I/O-connection
- Less than 0.41 mW / MHz power dissipation
- Fully automatic power-down mode
- Clock-off function
|Hyperstone's E1-32XSR
Note
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Hyperstone RISC/DSP
Various types
The Hyperstone E1-32X RISC/DSP family is available in various types. The external data bus-width is 32 bit and 16 bit for the E1-32X and E1-16X series, respectively. The package types for the E1-32X series are 144-pin TQFP (20x20x1.4mm) whereas the E1-16X series comes in a very compact (14x14x1.4mm) 100-pin TQFP package. Each type has 16 kByte on-chip RAM and maximum clock rates of 120 MHz unb 0.25 µm