Offering utmost customer benefit by combining a highly efficient processor and leading edge embedded technology? An ambitious goal - But this very combination of performance and innovation was indeed the ambition of Hyperstone from the outset.

Efficiency and customer benefit
Best performance with least effort: that's a definition of efficiency. At Hyperstone, this means maximum on-chip features at smallest silicon footprint.
We develop, very simply, chips that can do substantially more than others. Integrating RISC and DSP functionality into a single architecture: For highest performance and efficiency.
Our 32-bit RISC/DSP architecture is the most space-saving and therefore cost-effective solution on the market - Just look at the benefits:

• Space saving (many external peripheral elements are redundant)
• Low power consumption (smaller silicon area requiring less energy)
• Low Cost (only a fraction of total system cost)
• Decreased development time (integration is already done)
• Production efficiency (single unit tested - instead of testing many components)
• Process reliability (fewer components - therefore fewer failures)
• Decreased supplier dependence (fewer suppliers - therefore better availability)

Since our founding in 1990, Hyperstone has been a leader in the field of embedded technology. Many of today's standards first saw the light of day in our company. The result is that we are ahead of the competition - all of the time.
Here at Hyperstone, we consider our work as ‘embedded' in the production chain - efficiently:

• Logic design
  At the starting-point of the overall value creation chain, our team of highly qualified design engineers defines the intelligence of the subsequent product, the microprocessor or SOC.

 

• Back-end design and layout
  How will the chip ultimately turn out? The so-called "GDS II" data is prepared by key partners who specialise in this area such as iAd (Nuremburg), New Logic (Lustenau) and of course our parent CML (GB).

 

• Production of the wafer
  Silicon wafers on which the so-called "dies" are to be found: These dies are created in a lithographic process and form the heart of the subsequent chip. I.e. UMC and TSMC Taiwan, are long-established partners, since many years. These companies have guaranteed us any volume production we need, seven-digit numbers per month.

 

• Packaging and Testing
  Bonding the dies, so-called pads are bonded to the balls or pins of the housing. The dies are encapsulated in the package and the finished chips are tested once more: We use SPIL Taiwan due to their excellent performance record.

Guarantee: All of these well-known suppliers guarantee the quality our customers expect in their high-quality processor - all of the time.