Silicon IP Core

Our NAND Flash Memory Controllers are based on our 32-bit RISC/DSP Processor Core

NAND Flash Memory Controllers based on our 32-bit RISC/DSP Processor Core

Innovation that has been optimized, our core guarantees that safety and reliability are deeply embedded in the chip

Designing, developing and marketing Application Specific Standard Products (ASSPs) requires owning differentiated intellectual property (IP) to be implemented either in the silicon or the firmware. Implemented features in hardware are fast and energy efficient, whereas software is flexible. This optimal partitioning can make the difference.

The Hyperstone story starts in the early 1990s, with the introduction of the proprietary Hyperstone 32-bit RISC/DSP processor core, a breakthrough in terms of efficiency, gate-count and computational performance. Originally marketed as an IP for ASIC integration, this core now forms the heart of Hyperstone’s flash memory controllers. Over the years, the core has been optimized for specific NAND Flash management functions and algorithms. A unique scalable core as well as the ability to tune instructions allows for an optimal partitioning of features implemented either in hardware or firmware.

Balanced with the CPU core, standard flash management including frequent read and write functions are implemented in hardware in a so-called Direct Flash Access (DFA) unit. This co-processor handles dedicated operations and the interface to the flash. This also includes several encoding algorithms such as data-shaping, encryption and error correction code (ECC) parity calculations.

Included in the DFA, the Error Correction Code (ECC) unit is an important building block. Since error correction is a critical function to provide quality NAND Flash management, Hyperstone has the competence to develop and implement ECC internally. The ECC hardware that is implemented in the DFA needs to be tuned and must be compatible with NAND Flash requirements. The Hyperstone ECC is designed to support a wide range of different flashes. In order to minimize qualification efforts and maximize the controller life-cycle, ECC building blocks are designed to support different NAND technologies as well as future generations of NAND Flash.


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