Solid State bit density and the Flash Memory Controller

Solid State bit density and the Flash Memory Controller

Solid State bit density and the importance of the Flash Memory Controller

As we generate ever more digital data, the demand for mass storage is only going to increase.

Solid-state or Non-volatile memory is rapidly displacing magnetic media in mass storage, and this goes beyond the ubiquitous “thumb drive” to include high-density storage in servers. NAND Flash, the most prevalent form of solid-state storage, has many benefits, but increasing storage capacity and bit-density while maintaining sufficient reliability is a challenge for the industry. The Flash memory controller and its associated firmware play a crucial role in supporting developments in Flash-based mass storage.

Technological landscape

As a form of non-volatile memory, NAND Flash relies on a relatively simple principle known as the floating-gate cell. This is effectively a secondary gate added to an otherwise conventional MOSFET, but one that can be electronically altered to hold electrons even when power is removed. The process of moving electrons from the control gate and into the floating gate is called the Fowler-Nordheim tunneling effect, and it fundamentally changes the characteristics of the cell by increasing the MOSFET’s threshold voltage. This in turn changes the drain-source current that flows through the transistor for a given gate voltage, which is ultimately used to encode a binary value.

The Fowler-Nordheim tunneling effect is reversible, so electrons can be added to or removed from the floating gate, processes traditionally known as writing and erasing. However, the process does stress the physical cell and so the more times the cell is written and erased the more likely it is that the electrons stored in the floating gate will vary, causing errors when reading a cell and so reducing reliability. As memory density increases the physical implementation of each cell becomes smaller and fewer electrons are stored per cell, making data retention more critical. Although data is inherently binary, it still relies on transistors physics that has an analog behaviour. Digital electronics normally ignores the analog nature of transistors, but by embracing it, it is possible to encode more than just a 1 or 0 in a single cell. When it first emerged this process was termed “multi-level cell” (MLC), to differentiate it from conventional “single-level cell” (SLC) Flash. MLC typically refers to encoding four data states in a cell; 00, 01, 10 or 11, which can be represented by two binary digits. In effect this is achieved by more closely controlling the number of electrons stored in the floating gate. While density is increased, and therefore the cost-per-bit is lowered, MLC is normally slower than SLC and suffers from a greater bit-error rate and lower endurance.

Because of these benefits the technology has continued to develop, and we now have triple- and soon quad-level cell (TLC and QLC, respectively) NAND Flash memory. As the names suggest, a TLC can store three bits (one of eight values) while a QLC can store four bits (one of 16 values) in a single cell.

Future Technologies

As with MLC, the cost-per-bit drops significantly with every new technology, but endurance and performance suffer. For this reason, TLC and eventually QLC will probably be best applied in consumer applications for media storage, where endurance and performance are less important than cost. As these technologies develop, program/erase cycles, data retention and the impact of program disturb (unintentional programming of adjacent cells) will become more apparent. Again, it will fall to the Flash memory controller to handle the impact of these phenomena. 

Currently, all MLCs are planar-based (i.e. cells are built on silicon surface) and so subject to scaling limitations. To address this potential problem the industry is already looking at technologies that can guarantee storage densities increase beyond today’s limitations. One of the most promising is 3D Flash, where cells are stacked vertically, thereby avoiding the limitations of planar scaling. Two different 3D cell technologies are under development by Flash manufacturers. One is based on Floating Gate cell that can benefit from all the know-how accumulated with previous 2D production.  The second approach is based on “Charge Trapping” technology, which stores the charge necessary to encode a binary digit in an insulator layer as opposed to Floating Gate. One reason for this is that it is believed to simplify the manufacturing process, but it will undoubtedly require further innovations from Flash memory controller providers.


As we generate ever more digital data, the demand for mass storage is only going to increase. NAND Flash memory has the potential to provide increased memory density and a lower cost-per-bit, but puts pressure on the Flash memory controller to ensure maximum reliability even with newer Flash memory technologies